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Complete Three-in-One DDR Power Solution With BF_CUT
POWER MANAGEMENT Description
The SC2516 is a fully integrated, Three-in-One DDR Controller supplying power to the VDDQ, VTT and GMCH rails. Two synchronous buck controller provide the VDDQ and GMCH at high efficiency, while an internal linear regulator supplies the termination voltage with 1.8A(min) Source/Sink capability. The SC2516 uses the Intel(R) defined Latched BF_Cut signal to comply with motherboard state transitions. The regulator uses the 5VDUAL rail to supply VDDQ under all motherboard states, via the VDDQ switcher. The GMCH regulator is slaved off the 5V main regulator, using a separate UVLO on that rail. Additional logic and supervisory circuitry complete the functionality of this single chip DDR power solution in compliance with ACPI requirements. The MLP package with a copper pad provides excellent thermal impedance while keeping small footprint. VDDQ short circuit protection along with VTT current limit as well as two independent thermal shutdown circuits assure safe operation under all fault conditions.
SC2516
Features
Uses Latched BF_Cut from Intel Glue Chip to control regulators External VDDQ divider allows DDRI or DDRII Compatibility High efficiency VDDQ switcher External GMCH divider allows 1.5V or 1.25V programming High efficiency GMCH switcher supplies programmed output from the 5V or 3.3V rail Single chip solution complies fully with ACPI power sequencing specifications 1.8A (min) VTT Source/Sink capability High current 1Amp gate driver for VDDQ switcher Independent thermal shutdown for VTT Fast transient response Space saving 22-pin MLP package with copper thermal pad for heatsinking to PC Board
Applications
Power Solution for DDR memory per Intel motherboard specification High speed data line termination
12VCC 5Vdual
Typical Application Circuit
1 FBVDDQ SS/EN VTT 5 VDDQ 6 7 8 VDDQ 9 10 11 2 3 4
COMP FBVDDQ SS/EN VTTGND VTT VDDQ AGND VTTFB REFSENS TH _PAD FB_GMCH SS_GMCH
PGND BG TG BST 5VSBY COMP_GMCH BF_CUT TG_GMCH BG_GMCH GND_GMCH POK
22 21 20 19 18 17 16 15 14 13 12 GMCH Latched BF_CUT 3VCC 5VSBY FBVDDQ VDDQ
FB_GMCH ATXPWR_OK FB_GMCH
23
SC2516
Revision 8, May. 2005
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SC2516
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage, BST to AGND Standby Input Voltage Inputs AGND to PGND or LGND VTT Output C urrent Operati ng Ambi ent Temperature Range Operati ng Juncti on Temperature Thermal Resi stance Juncti on to Ambi ent Thermal Resi stance Juncti on to C ase Storage Temperature Range TG/BG/TG_GMC H/BG_GMC H D C Voltage TG/BG/TG_GMC H/BG_GMC H AC Voltage
Symbol V BST V 5V S B Y I/O
Maximum 20 7 5VSTBY +0.3, AGND -0.3 0.3
U nits V V V V A
o
IO(VTT) TA TJ JA JC TSTG
+/- 2 0 to 70 125 25 4 -65 to 150 BST + 0.3, PGND -0.3 BST + 1.0, PGND -4.0 t < 100 nS (measured from 50% to 50%)
o
C C
o
C /W C /W
o
o
C
V V
ESD Rati ng (Human Body Model)
ESD
2
KV
Electrical Characteristics
Unless specified: TA = 25 oC , 5VSBY = 5V
Parameter 5VSBY Voltage Qui escent C urrent BF_C UT Threshold P_OK Threshold 5VSBY Under Voltage Lockout VD D Q Feedback Reference VD D Q Feedback C urrent SS/EN Shutdown Threshold Thermal Shutdown Thermal Shutdown Hysteresi s
Symbol V 5V S B Y
C onditions
Min 4.5
Typ 5 12 8
Max 5.5 16
U nits V mA
BF_C UT low IQ(5VSBY) BF_C UT Hi gh 0.8 0.8 UVLO5VSBY VREF IFB VEN(TH) TJ-SHDN TJ-HYST VFB = 1.25V VD D Q/VTT @ Shutdown 2.4 1.238 -2 0.3
10 2.4 2.4 3 1.263 V V V V uA
TTL TTL 2.7 1.25
0.5 150 10
V
o
C C
o
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SC2516
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25oC, 5VSBY = 5V.
Parameter Switcher Load Regulation Oscillator Frequency Soft Start Current Maximum Duty Cycle Overcurrent Trip Voltage Top Gate Rise Time Top Gate Fall Time Bottom Gate Rise Time Bottom Gate Fall Time Dead Time Error Amplifier Transconductance Error Amplifier Gain @ DC Error Amplifier Bandwidth Error Amplifier Source Current Error Amplifier Sink Current Internal Ramp VT T LDO Output Voltage Source and Sink Currents Source and Sink Currents Load Regulation Error Amplifier Gain Current Limit
Symbol
Conditions
Min
Typ
Max
Units
IVDDQ = 0A to 10A fOSC ISS VSS = 800mV 225 20
0.2 250 25 75 275 30 80 80
% KHz uA % % nS nS nS nS 80 1.2 nS mS dB MHz 85 110 uA uA V
VTRIP TGR TGF BGR BGF td Gm AEA GBW
% of VDDQ Setpoint Gate capacitance = 4000pF Gate capacitance = 4000pF Gate capacitance = 4000pF Gate capacitance = 4000pF
70
75 25 25 35 35
20 0.8 RCOMP = open
50 1 38 5
FB = 0 , COMP = 1V FB = 1.5V , COMP = 1V VRAMP Peak - to - Peak
55 70
70 90 0.55
VTT IVTT IVTT VTT/ I AEA_VTT VTTILIM
VVDDQ = 2.500V VVDDQ = 2.500V VVDDQ = 1.500V IVTT =+1.8A to -1.8A
1.235 -1.8 -1.4 -1
1.250
1.265 +1.8 +1.4 +1
V A A % dB A
75 BF_CUT = low 3
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SC2516
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25oC,5VSBY = 5V.
Parameter GMCH Sw itcher GMCH Feedback Reference GMCH Feedback current Load Regulation Oscillator Frequency Soft start current Maximum Duty Cycle Top Gate Rise Time Top Gate Fall Time Bottom Gate Rise Time Bottom Gate Fall Time Dead Time Error Amplifier Transconductance Error Amplifier Gain @ DC Error Amplifier Bandwidth Error Amplifier Sink/Source Current Internal Ramp
Symbol
Conditions
Min
Typ
Max
Units
VREF_GMCH IFB_GMCH VFB_GMCH = 1.25V IGMCH = 0A to 5A fOSC ISS_GMCH VSS = 200mV
1.238 -2
1.25
1.263
V uA
0.2 225 8 250 10 75 275 12 80
% KHz uA % nS nS nS nS 120 1.2 nS mS dB MHz 90 uA V
TGR TGF BGR BGF td Gm A EA GBW
Gate capacitance = 2000pF Gate capacitance = 2000pF Gate capacitance = 2000pF Gate capacitance = 2000pF 50 0.8
40 40 40 40 85 1 38 1
VFB_GMCH = 0 - 1.5V, COMP = 1V VRAMP Peak - to - Peak
60
75 0.55
Pin Configuration
Ordering Information
Part Numbers SC2516MLTR(1) SC2516MLTRT(1),(2) Package MLP-22 MLP-22
Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free package. Device is fully WEEE and RoHS compliant.
Note: Pin 23 is the thermal Pad on the bottom of the device (c) 2005 Semtech Corp. 4 www.semtech.com
SC2516
POWER MANAGEMENT Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Pin Name COMP FBVDDQ SS/EN VTTGND VTT VDDQ AGND VTTFB REFSNS FB_GMCH SS_GMCH POK GND_GMCH BG_GMCH TG_GMCH BF_CUT Pin Function Compensation pin for the PWM transconductance amplifier for the VDDQ Switcher. Feedback for the VDDQ regulator. Connect to the VDDQ sense at the point of load. Soft start capacitor to GND. Pull low to disable controller. VTT return. Connect to copper plane carrying VTT return current. The trace connecting to this pin must be able to carry 2 Amps. VTT Regulator output. Regulates to 1/2 VDDQ. Sources or sinks 1.8 Amps. The trace connecting to this pin must be able to carry 2 Amps. VDDQ power input to VTT LDO. The trace connecting to this pin must be able to carry 2 Amps. Analog ground. Compensation components and the Soft Start Capacitor connect to this ground. Sense input for the VTT regulator. Connect to Point of Load for the VTT rail. Sense input for the VDDQ rail. VTT will be regulated to 1/2 of its voltage. Connect to Point of Load, where the VREF for the memory is generated. Sense input for the GMCH. Connect to Point of Load for the GMCH rail. Soft start for GMCH switcher . Connect a capacitor to GND. Connect to power OK signal from ATX power. Gate Drive return Ground for the GMCH regulator. Connect to Source of bottom FET. Bottom FET Gate drive for the GMCH regulator. Top FET Gate drive for the GMCH regulator. Latched BF_CUT input from Glue Chip.
COMP_GMCH Compensation pin for the PWM transconductance amplifier for the GMCH Switcher 5VSBY BST Connect to 5VSTBY input. The Top and Bottom Gate drive bus.Generated using bootstrap diode/capacitor. An additional diode is also required to trap the peak Bootstrap voltage for the BG drive. (see typical application circuit) Top FET gate drive. Bottom FET gate drive. Gate drive return. Keep this pin close to bottom FET source. Copper pad on bottom of chip used for heatsinking. It must be connected to ground plane under IC.
20 21 22 23
TG BG PGND TH_PAD
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SC2516
POWER MANAGEMENT Block Diagram
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SC2516
POWER MANAGEMENT Timing Diagram
VCC_Rail ATX _POK BF_CUT SS/EN TG BG VDDQ VTT SS_GMCH TG_GMCH BG_GMCH GMCH S5 S0 S3 S0 S5
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SC2516
POWER MANAGEMENT Application information
Description The SEMTECH SC2516 DDR power supply controller is the latest and most complete, Three in One switching and linear regulator controller, providing the necessary functions to comply with S3 and S5 sleep state signals generated by the Desktop Computer Motherboards. The SC2516 uses the Latched BF_CUT input signal which is generated externally on IntelR P4 Motherboard glue chip to comply with the power sequencing requirements. Logically, the BF_CUT signal can be represented as: Short Circuit Protection Short circuit protection is implemented by sensing the VDDQ output voltage. If it falls to 75% (typical) of its nominal voltage, as sensed by the FB pin, the TG and BG pins are latched off and the VDDQ switcher is shutdown. It will shutdown the VTT also, since the VTT regulator is fed from the VDDQ bus. To recover from the short circuit protection mode, either the 5VSBY rail has to be recycled, or the SS/EN pin must be pulled below 0.3V and released to restart VDDQ switcher operation. GMCH Power Section The SC2516 Switching controller supplies a 1.5V or 1. 25V GMCH (Graphic Memory Control Hub) voltage via a standard synchronous BUCK converter typically connected to the 5VCC or 3.3VCC power rail from Silverbox supply. Base on the basic advantage of switching mode controller, The GMCH output current can support up to 20A. Power Sequencing Since the Chip-Set supply should come up before the Active Memory cycle, the GMCH supply is sequenced with the rising edge of the P_OK signal from Sliver-box supply. Thus the GMCH regulator drivers are on when P_OK signal is greater than its respective threshold. The external MOSFET gates are pulled low when P_OK signal is lower than its threshold. Thus the GMCH is disabled during S3 and S5 (See timing diagram). VTT Rail The VTT termination voltage is supplied via an internal sink/source linear regulator when BF_CUT is low, and the P_OK signal has met its threshold voltage and SS/ EN voltage reaches to 1V. When BF_CUT is high, the VTT termination voltage is not needed and is thus tri-stated. The VTT linear regulator is capable of sourcing and sinking 1.8 Amps (Minimum). It is recommended that one should use at least 470uF low ESR capacitor and 1uF ceramic capacitor (from VTT pin to Ground with short distance) to ensure the stable operation. Short Circuit Protection The VTT regulator has two internal current limit circuits, one for the sink and one for the source regulators. Both current limits are set at 3Amp (typical). If maintained at current limit, the internal regulators act like constant current sources, and supply the max current until the device temperature raises above thermal shutdown thresholds, at which point that regulator shuts down.
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BF _ CUT = S 3 * P _ OK
(For details of the Latched BF_CUT signal definition, refer to Intel documentation). Where S3 is the input to the Silver-box Supply for Suspend to RAM, (S3=1 for Suspend to RAM) and P_OK is a signal generated by the Silver-box supply, indicating that all rails are within specification. S3 and S5 States During S3 and S5 sleep states, The operation of the VDDQ and VTT is governed by the intelR specifications with regards to the BF_CUT signal. The timing diagram demonstrates the state of the controller and each of the VDDQ, VTT and GMCH supplies during S3 and S5 transitions VDDQ Power Section SC2516 architecture eliminates the need for the BackFeed Cut MOSFET, since the VDDQ is always supplied from the same input voltage bus (5V dual). The SC2516 is capable of driving a 4000pf capacitor in 25ns (typical, top gate). This drive capability allows 15-20A DC load on the VDDQ supply from the 5V main input rail. Power Sequencing Once BF_CUT signal low and P_OK signal goes high, The VDDQ supply will be activated with S0 as well. The SS/ EN pin voltage is charged by internal constant current source. When SS/EN voltage reaches to 0.3V (typical), High side driver begins chopping and main power is activated as an asynchronous Buck converter. When SS/ EN voltage reaches to 1.25V (typical), Low side driver begins chopping and main power is activated as a synchronous Buck converter. When BF_CUT signal goes high (S3 state), the VDDQ switcher is always on and is sourced by 5VSTBY rail during this time. When both BF_CUT and P_OK signals are low, The VDDQ supply be disabled with S5 as well. Both high side and low side drivers are pulled low.
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SC2516
POWER MANAGEMENT Applications Information (Cont.)
Gpwm L EA R1 R Vbg 1.25Vdc Vin C Co Rc Ro R2
The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accomplish the goal: (1) Calculate the corner frequency of the output filter:
F o := 1 2 L C o
Fig. 1. SC2516 small signal model.
(2) Calculate the ESR zero frequency of the output filter capacitor:
F esr := 1 2 R c C o
Compensation design of the VDDQ Channel The control model of SC2516 VDDQ and GMCH section can be depicted in Fig. 1. This model can also be used in Spice kind of simulator to generate loop gain Bode plots. The bandgap reference is 1.25 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed gain of:
G m := 0.001 A V
(3) Check that the ESR zero frequency is not too high.
F esr < F sw 5
The compensation network includes a resistor and a capacitor in series, which terminates from the output of the error amplifier to the ground. The PWM gain is inversion of the ramp amplitude, and this gain is given by:
G pwm 1 V ramp
If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter. (4) Choose the loop gain cross over frequency (0 dB frequency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency :
F x_over F sw 5
where the ramp amplitude (peak-to-peak) is 0.55 volts . The total control loop-gain can then be derived as follows:
T( s ) T o . 1 s . R. C . . R. C s 1 1 s. R c. C o s. R c. C o L Ro
2 s . L. C o . 1
If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as:
Rc Ro
where
T o := G m G pwm V in R
F esr R := G pwm V in G m F o
1
2
F x_over V o F esr V bg
V bg Vo
when
F o < F esr < F x_over
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SC2516
POWER MANAGEMENT Applications Information (Cont.)
or
R := 1 G pwm V in G m
Step 1. Output filter corner frequency Fo = 1.6 KHz Step 2. ESR zero frequency: Fesr = 3.537 KHz
F o F x_over V o F esr F o V bg
2
when
F esr < F o < F x_over
Step 3. Check the following condition:
F esr < F sw 5
(5) The compensation capacitor is determined by choosing the compensator zero to be about one fifth of the output filter corner frequency:
F zero C Fo 5
Which is satisfied in this case. Step 4. Choose crossover frequency and calculate compensator R: Fx_over = 50 KHz
1 ..R .F 2
zero
(6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equations provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. (7) An additional capacitor should be reserved at the compensation pin to ground to have another high frequency pole. An example is given below to demonstrate the procedure introduced above. The parameters of the power supply (typical for VDDQ section) are given as :
Vin := 5 V Vo := 2.5 V Io := 20 A Fsw := 250 KHz L := 2.2 H Co := 4500 F Rc := 0.01 Vbg := 1.25 V Vramp := 0.55 V Gm :=
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R = 15 K Step 5. Calculate the compensator C: C = 33 nF Step 6. Generate Bode plot and check the phase margin. In this case, the phase margin is about 85oC that ensures the loop stability. Fig. 2 shows the Bode plot of the loop. Compensation design of the GMCH Channel The configuration of the PWM comparator of GMCH channel is such that its inverter input is connected to Comp_GMCH and the non-inverter input is connected to the internal ramp. The peak voltage of the internal ramp is 1.1V and the valley voltage is 0.55V. When COMP_GMCH voltage is below 0.55V, the maximum duty cycle will be generated by PWM comparator. If COMP_GMCH voltage is over 1.1V then the minimum duty cycle will be generated. To ensure proper soft start function of the GMCH channel, COMP_GMCH voltage must rise above 1.1V at the beginning of soft start period quickly. So a higher compensation gain is required. The following example shows that by choosing the compensation parameters as 15kOhm and 27nF for a typical output filter with 1~2uH inductor and 2000uF capacitor (ESR of 8~12 mOhm), the circuit will yield smooth soft start, stable control loop, and satisfactory transient response. The measured Bode plot of the loop gain is shown in Figure 3.
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0.001 A V
SC2516
POWER MANAGEMENT Applications Information (Cont.)
100 50 0 50 10 100
Loop Gain Mag (dB)
mag
( i)
3 1 . 10
4 1 . 10
5 1 . 10
6 1 . 10
Fi
Loop Gain Phase (Degree)
0 45 phase ( i) 90 135 180 10 100
3 1 . 10 4 1 . 10 5 1 . 10 6 1 . 10
Fi
Fig. 2. Bode plot of the VDDQ Channel
Fig. 3. Bode plot of the GMCH Channel
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12VCC C1 100p D1 D2 1N 4148 1N 4148 U1 15K 1 COMP FBVDDQ SS/EN VTTGND VTT VDDQ AGND VTTFB REFSENS T H _PAD FB_GMCH SS_GMCH TG_GMCH BG_GMCH GND_GMCH POK 15 14 3VCC 13 12 BF_CUT 16 COMP_GMCH 17 R5 15K 5VSBY 18 C9 BST 19 5VSBY 27nF C17 non pop. Latched BF_CUT C13 1uF C8 1uF TG 20 R3 BG 21 R2 2R2 2R2 D3 1N4148 C7 1uF PGND 22 2 3 C6 100n 4 5 C14 470uF C15 1uF VDDQ 6 7 8 VDDQ 9 10 11 C21 22nF FB_GMCH C16 1uF C5 2.2nF C4 33n FBVDDQ SS/EN VTT R1
5Vdual
C2 4.7uF Q1 IP D 09N 03
C3 1500uF
VDDQ L1 Q2 IP D 09N 03 1.5uH C10 1500uF C11 1500uF
C12
R4 1k
1500uF
FBVDDQ
Typical application Schematic
C18 1uF
C19 IP D 09N 03 Q3 23 4.7uF
C20 1500uF
SC2516
ATXPWR_OK
R7
2R2
1.5V GMCH L2 Q4 IP D 09N 03 C22 1000uF R9 2R2 C23 1000uF 1.5uH
POWER MANAGEMENT
R8 200R
R10 FB_GMCH 1K
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R6 1k
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SC2516
12VCC
5Vdual
Application Schematic for Intel Broadwater platform
1N 4148
1N 4148
C1 100p D1 U2 15K 1 COMP PGND BG TG BST 5VSBY COMP_GMCH BF_CUT TG_GMCH BG_GMCH T H _PAD GND_GMCH POK 15 14 16 17 R5 15K 18 C9 19 5VSBY 27nF C17 non pop. Latched BF_CUT C13 1uF C8 1uF 20 R3 21 R2 2R2 2R2 D3 1N4148 FBVDDQ SS/EN VTTGND VTT VDDQ AGND VTTFB REFSENS FB_GMCH SS_GMCH 22 2 3 C6 100n 4 5 C14 470uF C15 1uF VDDQ 6 7 8 VDDQ 9 10 11 C21 22nF C18 1uF C16 1uF C5 2.2nF D2 C4 33n FBVDDQ SS/EN 0.9VTT R1
C2 4 .7u F Q1 IP D 05N 03LA
C3 1500uF
1.8VDDQ C7 L1 1uF Q2 IP D 05N 03LA C10 1500uF C11 1500uF C12 1500uF 1.2uH
C26
C21
R4 442R
10uF
10uF
FBVDDQ R6 1k
3VCC 13 12 IP D 05N 03LA Q3 C19 4.7uF C20
23
SC2516
ATXPWR_OK
1500uF
R7
2R2
1.25V GMCH L2 IP D 05 N 03LA Q4 R9 2R2 1.2uH C22 2200uF C23 2200uF C24 10uF
FB_GMCH
POWER MANAGEMENT
C25
R8 0R
FB_GMCH
10uF
R10 non. pop.
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SC2516
SC2516
POWER MANAGEMENT Outline Drawing - MLP-22
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SC2516
POWER MANAGEMENT Land Pattern- MLP-22
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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